1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating semiconductor device, more particularly, to a semiconductor device with non-volatile memory and logic transistor and fabricating method thereof.
2. Description of the Prior Art
A typical NVM integration circuit generally has structure including a non-volatile gate stack along with logic gate stacks. Recently, high dielectric constant metal gate (HKMG) scheme has been developed for the logic gate stacks. In a conventional replacement metal gate process of HKMG scheme, at least two chemical mechanical polishing (CMP) steps are utilized, wherein the first CMP step is performed prior to removing dummy polysilicon gate stacks and the second CMP step is performed after the deposition of the metal gate stacks is complete. These two CMP steps require that the upper surfaces of the gate stacks be coplanar. However, in consideration of applying HKMG scheme to the NVM integration circuit, the gate stack of the usual NVM cell is taller than the logic gate stacks, thus the formation of NVM cell is incompatible with the HKMG scheme.